Performance Analysis of N-Type Gated Diode Three-Transistor DRAM in 180nm Technology

Author Name(s): Prof. Yogesh N. Thakare, 2Dr. Sujata N. Kale
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In this paper three-transistor n-type gated diode DRAM cells have been designed and analyzed. In this design storing capacitor is replaced by n-type gated diode to improve memory read/write operation. In today’s world to store digital data, demand of semiconductor memory increases day by day. Generally in embedded DRAM, SRAM is widely used because of its high speed of operation, high noise margin and good logical compatibility. But, SRAM cell consists of six transistors; hence its cell area gets increases and also consumes more power. So, a novel solution has been proposed in this paper to replace capacitor in DRAM by n-type gated diode. Design of 3T-1D DRAM cell is compared with different input voltages and different technologies to calculate power dissipation.

Keywords Power Dissipation, SRAM, DRAM, Gated Diode


Day by day, world demand for large data storage capacity chips in small size. Hence the design becomes scale down day by day. In most of hand held devices consist of SRAM as a memory storage device because of its high speed of operation. This memory is further divided into volatile and non-volatile memory. Non-volatile memory is further classified into read only memory, magneto-resistive random access memory and flash memory. Volatile memory is further classified as static memory and dynamic memory. The SRAM consist of latch hence data was retained as long as power is turned on whereas DRAM cell consists of capacitor to store binary information and transistor to access this capacitor.


The DRAM Cells have many advantages as compared to SRAM Cells. The 3T-1D DRAM cell performance is analyzed at different voltage levels and at different technology parameters using Tanner EDA tool. In comparative analysis of 3T-1D DRAM, it is observed that as the technology parameter and input voltage decreases, the power dissipation also goes down. Further research can be carried out to get high stability, reduce retention time and the ability to tolerate performance variation. This approach provides a comprehensive solution to many of the issues that will impact on-chip memory design in nano scale process technologies.

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