Design of Lookup Table using Quaternary Logic in Voltage Mode Standard CMOS Circuit

Author Name(s): Amruta S.Jadhav, Shweta Hajare, Pravin Dakhole
Author Email: amrutajadhav599@gmail.com

Abstract

Designer face challenges in interconnection due to the large number of components. Interconnection and power consumption perform significant part in this paper. The shortcomings of the previous work done is high interconnections, which leads to high power usage along with more area required. The Binary logic circuits is constrained by using the number of interconnections, which increases the delay and power consumption with the boom in logic. So we design new techniques that is going to reduce the interconnection of the circuit as well as the power consumptions. Multiple-valued logic can decrease the number of required interconnections. In this paper we use quaternary to binary decoder to reduce the multiplexer control lines is the vital parts of the processing component and therefore it has a focal point of research. Therefore, the design of adders through multiplexer using multi valued logic can show to be very beneficial. So we introduce and full adder based totally at the designed quaternary lookup table.

Introduction

In Traditional binary CMOS advanced circuits, static power utilization has its linkage to outflow current, and dynamic power consumption is given by equation 1 given underneath (1), where C is the capacitance of the node being determined and VDD is the power supply voltage PD α CV2DD — (1) The CMOS process moved a long way by shrinking the transistors (thus dropping C) and using lower supply voltages (Reduced VDD), leading to low power and high integration scenario. This capacitance C includes the directing capacitance of interfacing wires as well. It has been stated that routing overstep transistors impact for latency and power dissipation of design in current CMOS forms [1].

Conclusion

Voltage Mode CMOS multivalued design understanding using quaternary lookup table (QLUT) gain attention due to its striking characterization and performance factor. The proposed design of half adder & full adder using quaternary logic has better function as compared to binary logic. The transistor count is less and the power dissipation is 1.12 mW for half adder and 3.08mW for full adder.

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