Design of Carry Skip Adder using Concatenation and Incrementation Schem

Author Name(s): Puja Ramesh Khunte, Monica Kalbande, Tejaswini G. Panse
Author Email: poojarkhunte@gmail.com

Abstract

In Today’s digital world biggest challenge is to reduce delay for increasing speed and efficiency of digital devices. In carry skip adder to achieve high speed we need to lower the path delay. Where, the carry generated should be driven to the output as fast as possible, thereby in results reduces the worst path delay which determines the ultimate corresponding speed of the digital structure. In Conventional Carry Skip Adder (Conv-CSKA), the speed enhancement parameter can be achieved by using concatenation and incrementation schemes. In this paper to achieve high speed, multiplexer logic in Conventional CSKA structure is replaced by AND-OR-INVERT (AOI) and OR-ANDINVERT (OAI) compound gates.

Introduction

Adders are necessary and one of the most extensively used component in the digital integrated circuit design. Adder is key building block in Arithmetic and Logical Unit (ALU) and play a major role not only in addition operation but also in multiplication, subtraction operation. Speed, Power Dissipation, Area, Delay and Energy consumption these are vital points taken into consideration while designing any adder and it strongly affect the performance of processors. The carry skip adder (CSKA) is the adder which has area optimized structure that has greater speed with lower energy requirement. In carry skip adder time required to propagate the carry is reduced by skipping over a group of consecutive stages of adder. To reduce critical path delay of adder the standard carry generates propagate logic is used and for less power consumption ripple carry blocks are used. The delay can be balanced by using the ‘generate propagate’ logic along with the number of inputs to the skip logic which limits the critical path delay.
There are number of different adder’s family available in digital world and they are categorized by their respective different parameters like delays, energy consumption, power consumption, area usage and number of transistors. Examples of
different adder’s families are Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Carry Increment Adder (CIA), Carry Skip Adder (CSKA) and Parallel Prefix Adders (PPAs). The Ripple Carry adder (RCA) is a simple adder which has simple design structure with lowest area and less power consumption but with one drawback of worst critical path delay. In Carry Select Adder (CSLA) some parameters like area required, speed and power are significantly larger than those of the RCA parameters. In case of Parallel Prefix adders (PPAs) which is also named as Carry Look-Ahead Adders, exploits direct parallel prefix structures to produce the carry as fast as conceivable. In Parallel Prefix adders there are number of altered types of parallel prefix algorithms with different performances. It should be noted that if we compare other adder’s family with PPAs then the structure complexity of PPAs is higher than others adder’s family.

Conclusion

In this project we design the Conventional Carry Skip Adder (CSKA) and Proposed Carry Skip Adder(CI-CSKA) using cadence virtuoso design tool. In CI- CSKA to enhance the speed of adder we modify Conventional CSKA by replacing 2:1 MUX by AOI/OAI compound gates and by using incrementation block. Proposed structure uses Concatenation and Incrementation Scheme for higher performance. The results shows that the CICSKA structure is a good adder compare to conventional CSKA for the applications where high speed and low power consumption with lower PDP are required.

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