**Author Name(s):***K.A.Jyotsna, P.Satish Kumar, B.K.Madhavi

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## Abstract

This work represents a novel approach for implementing a VCO Based ADC using Current Mode Logic (CML). It primarily focuses on applicability of CML logic for building digital circuits and systems that run at very low voltages. Many ADC’s require low power, high speed with less area and delay. The need for this low power, small delay, area efficient and high speed ADC is pushing towards the use of Current Mode Logic (CML). The VCO Based ADC was designed in 45nm technology at a power supply of 1V using cadence tools. The VCO was implemented using the 8 stage Differential Delay Cell. VCO is followed by 16 1-bit Reset Counters and a 16-bit Adder. The Reset Counter consists of One Divider, Two D Flip-flop’s and an XOR gate.

## Introduction

Many modern day applications like mobile systems, sensor networks, implantable biomedical systems like cardiac pacemakers ,wearable battery powered systems need circuits work with ultra low power consumption with less sensitivity to supply voltage ,temperature and process variations. For all these circuits performance plays a secondary role [1].

The best welcomed alternative for conventional CMOS logic is Current Mode Logic which is useful for designing ultra low power circuits. This logic is good for very low bias currents and delivers good control on power consumption of each gate. It operates at very low supply voltages without any affliction to the system performance. The speed and power consumption of this logic can be adjusted by altering the bias current of the gates without the need for resizing the devices. CML techniques provide large static power consumption due to their constant current operation. At different frequencies, their dynamic power dissipation is constant.

A novel MOS Current Mode Logic (MCML) approach for implementing VCO based ADCs is proposed in this paper. Section II explains the motivation for MCML circuits. Section III describes the VCO based ADC architecture and its different blocks and Section IV reports the implementation and results while section V summarizes conclusions.

Current Mode Logic:

Current Mode Logic (CML) is the digital implementation of differential amplifier circuit. It uses differential NMOS transistor pairs to switch a constant bias current towards one of the 2 branches constituting the two terminals of the differential output signal as shown in the fig 1 [2]

## Conclusion

By designing the VCO Based ADC using current mode logic (CML) digital logic gates in transistor level schematic are designed and operated at a bias voltages of V_{BN }of 0.5V and V_{BP }of 0.8V with VDD of 1V power supply . In CMOS technology, the logic levels for logic 0 is 0V and logic 1 is 1V but in the case of CML logic by using these above bias voltages the output of the logic levels for logic 0 is 0.248V (voltage swing) and logic 1 is 0.96V which is an advantage. Another advantage of CML compared to CMOS is the number of transistors will be less, it has less delay so more speed of operation and also consuming very low energy per computation. Thus the CML-based digital systems are highly suitable for designing the digital parts of the VCO Based ADC. The schematics are drawn using cadence virtuoso, schematic editor, symbol editor and while the simulations are done using Analog design environment (ADE L) Tools. The overall power and delay of VCO based ADC is 622.7mW and 484.5ps.

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