Design of 32 Bit Data path Unit of ARM7 Microprocessor using Sub threshold Current Mode Logic

Author Name(s): K.A. Jyotsna, P. Satish Kumar, B.K. Madhavi, Sana Bano
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In the present days, Very Large Scale Integration (VLSI) is focused upon designing energy efficient electronic devices. These are nothing but the embedded gadgets whose core is a processor. Advanced RISC Machine (ARM) is one of the families of computer processors which have an reduced instruction set architecture. Current Mode Logic (CML) is one of the low power logics which is used to design circuits with an extended battery life.  The circuits built using this technique are capable of giving a dependable and sturdy system.  In this paper, the proposed ARM7 microprocessor has been designed using the Sub threshold Current Mode Logic (STCML). All the design blocks operate in the sub threshold region at 0.24V power supply. The Data path of ARM7 has been implemented using Cadence Virtuoso Tool in 45nm technology.  The results of the blocks have been viewed on Spectra Simulator and the power and delay calculations have been computed. The propound microprocessor is capable of finding place in DSP and other Embedded applications.


Power Dissipation is a major issue in most of the VLSI circuits whose cause is increased leakage currents and with the increasing number of transistors per unit area, this becomes more prominent. This might lead to large amount of heat-dissipation from the device which may cause its failure. When the low power application of devices is kept in view, RTL level optimization is required.[1] This is essential to obtain portable devices and those which have longevity in terms of battery life.

The CMOS technology contributes to large number of leakage currents in the transistor out of which Sub threshold leakage current is predominant. This leakage current contributes to the major part of the power dissipated by the transistors. Current Mode Logic (CML) also known as Sub threshold Source Coupled Logic (STSCL) helps the digital circuits to be operated in sub threshold region with reduced leakage currents and meager power consumption.[2],[3]

Microprocessors also known as single chip computers are the elementary units of information systems. Their performance has been driven by the transistor speed, energy scaling and also by the micro architecture gains advances. These advanced micro architectures have stationed transistor integration capacity, pipelining etc. to furnish increasing performance.

ARM microprocessors are the most ubiquitously used Instruction Set architectures in terms of quantity produced. ARM architects the insidious intelligence that is transfiguring our daily experience. In the world, more than 95% wearable’s work on ARM delivering advanced signal processing capabilities. With the integration of ARM and low power logic, energy efficient devices which meet innovative market demands can be developed.

This paper is formed as follows Section II presents the literature review on Current Mode Logic, STCML and ARM7 Section III presents the Implementation of Datapath components of ARM7, Section IV furnishes the Simulation Results of all the Data path blocks of ARM7 in Cadence Virtuoso Tool and also the  Comparison of Power and Delay with voltage scaling is presented. Finally, Section V draws the Conclusions for the proposed methods.


This paper presents an innovative power efficient methodology for the design of Data path components of ARM7 microprocessor using Cadence Virtuoso in 45nm technology with 0.24V power supply. It can be inferred from the power calculations that when the voltage scaling is done the power consumption has reduced without causing any effect in the correctness of the waveforms. Also, this method has proved to be efficient for the design of ARM7 and also created room to incorporate the Sub threshold Current Mode Logic with other low power logics   in order to reduce the power consumption further if desired.

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