Design Analysis of SRAM cell with improved Noise Margin based on Aspect Ratio Adjustments

Author Name(s): *Y.Alekhya, J.Sudhakar
Author Email: alekhyayalla@gmail.com

Abstract

Due to increasing demand for faster memory devices, SRAM has gained importance for research focus. SRAM cells have various applications like SRAM based LUT in FPGA, DSP applications, electronic subsystems of telecommunications etc. As the technology scales down the threshold voltage is lowered, leading to less margin to noise and disturbs the SRAM cell stability .The proposed work investigates on the CMOS based memory cell in submicron regions analyzing the static noise margin during active operations and improves the cell stability.

Introduction

The SRAM cell stability determines the soft-error rate and the sensitivity of the memory to process tolerances and operating conditions. To analyze static cell stabilities Static Noise Margin (SNM) simulations have become dominant method to assess the cell reliability in high density memories [1]. The focus of cell stability on SNM analyses of SRAM cells have mostly restricted to the simulations, however, some works discuss this through providing analytical expression [2,9]. This work deals with the SNM of SRAM cell both from analytic as well as simulations point of view. The advantage of mathematical representation is that it explicitly expresses the SNM as function of different cell parameters such as supply voltages, pre-charge voltages, bit line voltages, and source voltages.

Conclusions

Nano scaled technologies for low power and high speed applications degrades the stability which is measured by static noise margin. From the above analysis, it can conclude that the reliability of 6T SRAM cell can be effected with operating supply, pull up ratio and cell ratio. At different variation in cell ratio and pull up ratio the RSNM and WSNM has improved at dynamic supply voltages. This shows that the 6T SRAM cell operate efficiently in sub threshold regions.

References

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