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True random number generator finds applications in cryptography, communications, industrial testing, computer games, random padding and Monte Carlo simulations. Software based random number generators suffers from higher delay due to serial execution of codes, low quality due to correlated data, low throughput and large processing time. FPGA based random number generators are efficient due to parallelism and bit wise operation. In this paper, an attempt has been made to evaluate the performance of the true random number generator based on beat frequency oscillators using FPGA. Asynchronous modulo ‘D’ counters are explored as beat frequency oscillators. Varying the value of D for both the asynchronous clock divider units along with maintaining higher frequency at oscillator X, adds to the randomness of the generated bit streams. Clock frequency divider ‘D’ can be selected from the set of values stored in memory. One of the most important advantages of the beat frequency based true random number generator is its tunability through controlling parameter, partial reconfiguration, placement and routing. The technique does not depend on the type and manufacturer of the FPGA, placement and routing in the process of implementation and requires low hardware footprint. Mathematical model, VHDL simulation and experimental results of the true random number generator are discussed. The proposed architecture for TRNG was simulated using VHDL through Xilinx ISE 14.1 software platform and implemented on Virtex 5 XC5VLX20T FPGA device. The random bit stream passes the entire NIST statistical test suite.
Keywords True Random Number Generator, Beat Frequency Oscillators, FPGA, NIST
Tremendous development in the digital technology and Internet of Things (IoT) has fuelled the use of security components such as cryptography, password generation, authentication, ownership, copyright protection and key generation. True random number generator (TRNG) is the essential module in most of the above blocks. TRNG finds applications in cryptography, communications, industrial testing, computer games, random padding and Monte Carlo simulations. TRNG circuits exploits a random process, the source of randomness is mostly through noise, which is extracted, amplified and digitized. Finally a post processing module provides a uniform statistical distribution of the extracted bit streams. Hardware implementations of TRNG are found to be more advantageous with respect to delay, quality, throughput and large processing time as compared to software implementation  . Field programmable gate array (FPGA) has emerged as the best platform for the implementation of TRNGs due to parallelism, bit wise operation and low cost. Besides being prototyping devices, FPGAs are also explored for cryptography applications. Hence many embedded cryptography systems requires better quality TRNGs implemented on FPGAs . However, the biggest disadvantage of the FPGA lies in the resource constraint environment that includes digital logic blocks and does not incorporate analog blocks. Hence the only source of randomness lies in the metastability and jitter. It makes the design and implementation of TRNGs more challenging and difficult using FPGAs. It is essential that FPGA implementation of TRNGs should be independent of the technology, manufacturer and implementation process.
Fully digital true random number generator based on beat frequency oscillators, jitter and asynchronous modulo counter using FPGA is demonstrated. Bit wise operation was explored through asynchronous modulo counter and its divider parameter D that facilitates to select operating clock frequency of the oscillators. It assists in introducing randomness into the circuit and provides partial tunability. Asynchronous modulo counter can be successfully replaced with ring oscillators and PLL to explore device independent operation. Although the use of memory and its controller increases hardware footprint marginally, but can be easily accommodated in a FPGA. It also provides additional tunability and control over the circuit through parameters. Further the functionality of the circuit can be scaled by increasing number of flip flops in modulo counter, which may improve statistical properties of the random numbers. Also the vulnerability of the circuit can be tested for various attacks.
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