Power Aware Multiprocessor System on Chip (MPSOC) Based on Dynamic Frequency Scaling of Soft Core Processors

Author Name(s): Mitali Patel, Jitendra B Zalke, Sandeep Kumar Pandey, Anuradha D Verma, Ruchir V. Nandanwar
Author Email: mitalip886@gmail.com


Today’s portable Embedded systems need less power consumption to satisfy today’s applications needs, like smart phones, laptops, tablets etc. An option for implementing the power aware multi processor system is to introduce the concept of on demand clock scaling of multi processor system. The proposed work presents an implementation of on demand clock scaling of a multiprocessor system on a chip. The proposed architecture uses the Digital Clock Manager (DCM) of the FPGA to change the clock of the soft-core processor. Each soft-core processor in the architecture is allowed to scale the frequency through clock control unit. The clock control unit is responsible for tuning or scaling the clock frequency of processors on demand or according to the application requirements. The entire system is implemented using MicroBlaze soft core from Xilinx and tested on Vertex-5(XUPV5-LX110T) FPGA development board with Xilinx EDK.

Keywords DCM, MicroBlaze, PE, DFS.


Today’s embedded systems need more computational power to satisfy modern applications needs, like image processing, audio/video encoding and decoding, etc. and parallel processing using multiprocessor systems on a chip (MPSoC) are an option to deal with this increasing computational needs [1][2][3]. MPSoC environment are created by connecting two or more processors together. The MPSoC environment may be based on multi-core or multi-processor. If different CPUs are sharing the same cache memory module then they are referred as multi-core, and different cache for different CPUs are termed as ‘multi-processor’ (MP). An MPSoC is a multiprocessor on a single silicon chip. It contains more than one processor memory modules (PMMs) and may contain ten or even hundreds of processor-memory modules (PMMs). The term many core architecture is used for hundreds of cores and more on the same chip that are connected together by appropriate means of communicating bus. Fully custom-designed chips have traditionally implemented MPSoCs, multi- and many-core architectures. During the last few years the capabilities of Field Programmable Gate Arrays (FPGAs) have increased significantly and thus FPGAs allow the implementation of these architectures as an alternative, although with less powerful PMMs today [4].


508 total views, 1 views today

Download PDF File

About the author: admin