Design and Implementation of Reconfigurable Modulator Using FPGA for Cognitive Radio System

Author Name(s): Oveek Chatterjee, Dr. Rajeshree Raut, Rvanjit K.Sawant
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With the increase of smartphones and laptops, number of users using communication systems is increasing day by day exponentially. The frequency spectrum required for these systems is limited. Thus in order to increase the proper utilization of the spectrum, cognitive radio technology is being developed. In this system, spectrum is shared between the primary (licensed) users and secondary (unlicensed) users. Secondary user uses a channel only when it is not being used by the primary user. Also different channels require different modulation techniques based on the noise present in their respective channel. Thus, a secondary user transmitter should be able to cope up with this requirement. In this paper an assumption has been made on the channel selection by frequency reconfiguration, so the paper focuses on the reconfiguration in digital modulation scheme. A way of designing and implementing reconfigurable modulator system using FPGA is discussed in the paper. Different types of noise present in the channel are detected with the help of Fourier transform and decision is taken to dynamically switch between different digital modulators. Keywords Cognitive Radio, FFT, BASK, BFSK, BPSK, Microblaze Processor, FPGA


We cannot increase the spectrum beyond a certain range because of various environmental and health hazards. Thus, to increase the proper utilization of the available spectrum, dynamic allocation of the spectrum was proposed [1] in contrast to the most widely used static spectrum allocation method. In dynamic spectrum allocation a channel is allocated to a secondary (unlicensed) user when a primary user is not using the channel with the help of a cognitive radio system, proposed by Joseph Mitola [2]. The cognitive radio cycle consists of four main stages [3]: 1. Sensing: It is monitoring the available spectrum and scanning for vacant channels. 2. Analysis: It is analysis of the available vacant channels and reaching a conclusion of allocating one of the vacant channels to the secondary user based of the properties and characteristics of the secondary user and the channel. 3. Reasoning: In this stage of the cognitive cycle, the ways of adapting to the characteristics of the channel are sorted out and the required parameters are set. 4. Adapting: Finally at this stage the secondary user dynamically switches to the new parameters as required by the channel.



It can concluded from the above sections that both, the noise detecting system and the designed modulator architecture works as expected in detecting any noise present in the particular channel and performed required reconfiguration in the modulation system. The future scope of the system is as follows: • The input signals for both the noise detecting system and the reconfigurable modulator can be made dynamic by interfacing external ADC to the system and thus the input and the control signals required can be obtained by function generators or any other signal source as per the requirement. The noise detecting system can be made more robust by measuring the Euclidean distance in the constellation diagram. • The basic modulator systems can be replaced with widely used modulator systems such as M-PSK and QAM modulation techniques to fit the system for real world application. • A timer can be included in the design and used as interrupt to calculate the clock cycles required for the Ccode used in the system to further optimize the performance of the system. • Moreover, in order to optimize the resources required the different modulator sub blocks can be implemented using a single sub block with the help of partial reconfiguration provided by the Xilinx partial reconfiguration tool [8].

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