Design of High Performance Low Leakage FPGA Slices using Control Logic

Author Name(s): Esther Rani Thuraka, Raghava Katreepalli
Author Email: estherlawrenc@gmail.com

Abstract

Field Programmable Gate Arrays (FPGAs) are significant in digital designs, Scientific Computing, Digital Signal Processing and Tele-communications. To use re-configurable technology in the portable applications, the devices that consume significantly less power and programmable are essential. In FPGAs, leakage power has become a major component as the technology evolves to deep sub-micron. An effective way to reduce leakage power is to parallelly employ both Power Gating and MTCMOS techniques in the designs. The elementary impression is design of Re-Configurable Look-Up Tables (LUT) in which logic gates are controlled by sleep transistors to reduce the leakage power. For turning off logic gates, the input of the sleep transistor is controlled by a control signal. A 4-bit Arithmetic Logic Unit (ALU) is designed with these LUTs and found that power dissipation is reduced by 40%. The control signal is given in such a way that the non-used blocks of the design are completely turned off by using Power gating technique and the leakage power is reduced by using MTCMOS technique. LUTs are designed in CADENCE Virtuoso Schematic Editor and simulated for verification in Analog Design Environment.

Introduction

FPGA is a field programmable Integrated Circuit (IC) that can be programmed after fabricating the device. As per the Hardware Description Language (HDL) code the gates involved in the design are connected.  Devices that consume very less power and reconfigurability are most important in new programmable devices. FPGAs cannot be used in mobiles as they have limitations because of their high-power consumption. Compared to Application-Specific Integrated Circuit (ASIC) implementations, FPGA implementations have more power overhead. A very high speed I/O and data buses are used in FPGA designs therefore verification of setup time and hold time is a complex task. During floor planning the resources allocation within FPGA take place and time constraints are met. FPGAs can be used to implement any logical function that an ASIC could perform.  FPGAs hold considerable promise as fast to market replacement for ASICs in many applications. Even after applying low power design techniques, the power consumption of FPGAs remains unaffordable. Earlier techniques to reduce the power dissipation of FPGAs, focused on both dynamic and static power of these devices [1]. In hand-held devices like mobile phones the leakage power will be even more significant, since these devices are often used in an ‘always on’ state, remaining idle excluding for short bursts of activity [2].

ICs reduced system complexity, manufacturing cost and improve performance. They are relatively very expensive to develop and time to market is more. FPGAs were introduced as substitute to custom ICs for implementing entire system on a single chip and to provide the convenience of re-programmability to the designer and user. FPGAs can offer high density designs compared to discrete small and medium scale components. FPGAs take small amount of time for implementation with the help of Computer Aided Design (CAD) tools. Time taken for Physical design and mask preparation steps can be saved in case of FPGAs

Conclusion

The power consumption which is the key factor in the design of FPGA is greatly reduced by using re-configurable LUTs driven by control logic. Both dynamic and leakage power is reduced by using re-configurable LUTs. Among the  pool of LUTs present in FPGA, when re-configurable LUTs are used along with control logic, only the required LUTs are ON and remaining LUTs are maintained in OFF position by using control inputs. This reduces the dynamic power consumption. During standby mode of the design, the LUTs remain off by a sleep transistor which is present between pull-down circuit and the ground terminal resulting the further reduction of the leakage power. Presence of sleep transistor for every logic gate will increase the area of the circuit at same time reducing power consumption by more than 40%. This type of logic where only required logic gates are used while others remain in unused state, is very useful in systems where power consumption is the dominating factor. The control input for sleep transistor may be applied by scripting tools with supporting algorithms which can ease the control input to the LUTs by programmed logic to the FPGA.

 

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