Design and Assessment of Type-II PLL implementing Various CMOS PFDs

Author Name(s): Neelima Koppala*, G. Madhavi Latha, N. Suguna
Author Email:

Abstract

This paper reflects the design and comparison of different Phase Frequency Detectors (PFD) used in Phase Locked Loop (PLL) using different logic gates. A PFD plays a major role in PLL, it detects both phase and frequency of a signal. In this paper a PFD is implemented using three different gates like AND, NOR and NAND gates. An AND based PFD produces accurate results and eliminate-s the missing edge and phase ambiguity problems, where NAND based PFD generates moderate output and its can be implemented using less number of transistors so the power dissipation will be less when compared with the AND based PFD but the RMS noise is high. Finally by using the NOR based PFD generates accurate results with less power dissipation and reduced RMS noise and it eliminates the missing edge and phase ambiguity problems. In this paper three PFDs are compared in terms of quality of the output, power dissipation and the RMS noise. These PFDs are implemented in Type-II PLL with design of charge pump, low pass filter and voltage controlled oscillator. The parameters calculations and the observation of waveforms are done using the Mentor Graphics Tool.

Introduction

A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. It consists of a phase detector, low pass filter and a VCO as shown in figure 1[14]. It selects the intended channel with minimum distortion. The phase detector is a circuit that normally has an output voltage with an average value proportional to the phase difference between the input signal and the output of the VCO. It is used as an “error amplifier” in the feedback loop thereby minimizing the phase difference. An Exclusive-OR (XOR) logic gate can be used as a phase detector. The low-pass filter is used to extract the average value from the output of the phase detector [1] [2]. This average value is then amplified and used to drive the VCO. The negative feedback of the loop results in the output of the VCO being synchronized with the input signal. Depending on the type of the phase-locked loop, the output of the oscillator mayor may not have a phase difference compared with the phase of the input signal. It is used in CMOS transceivers for tuning of signals [3][4].  The figure 1 represents the phase detector which generates pulses at regular intervals of time due to which a finite phase error exists. To nullify this error, we must change the frequency of the VCO or allow the VCO to accumulate phase faster (or more slowly) than the reference so that the phase error vanishes or change the frequency back to its initial value. Basically for practical circuits, negative feedback loop is used. The PD produces repetitive pulses at its output, modulating the VCO frequency and generating large sidebands, so we interpose a Low Pass Filter in between phase detector and voltage controlled oscillator to suppress these pulses.  The combination of phase detector and low pass filter is replaced by a frequency detector that generates a dc value in proportion to the input frequency difference. The FLL may also suffer from a finite error if its loop gain is finite or if the frequency detector exhibits offsets. Hence type-I PLL suffers drawbacks like less stable loop, limited acquisition range and finite static phase error and its variation with input frequency. As an alternative, we use type-II PLL practically which is shown in figure 2. It consists of a PFD, Charge pump, Low Pass Filter and Voltage Controlled Oscillator.

Conclusion

The PLL is the device used for tuning to the required frequency range of the receiver. It consists of three circuits, i.e., phase detector, low pass filter and a VCO. The Type-I PLL suffers from less stable loop, limited acquisition range and finite static phase error and its variation with input frequency. Hence Type-II PLL is considered for practical designs which has Phase Frequency detector, Charge Pump, Low Pass Filter and Voltage Controlled Oscillator. Among these PFD plays a important role, in extracting the phase of the receiving signal in line with the reference signal. A PFD is a circuit that senses two periodic inputs and produces an output whose average value is proportional to the difference between the phases of the inputs. Basically it is implemented by using XOR gate, but this gate consumes more area and power. This paper deals with design of PFD using three different logic gates like AND, NAND and NOR gates. The PFDs are operated at 150MHz frequency and with the supply voltage of 3.3V. To analyze the RMS noise the Vdiv is taken as a sine wave with 3.3V as amplitude with 150MHz frequency and the Vref is nothing but a pulse signal with 3.3V amplitude and with a dc supply voltage of 3.3V. From results, it was observed that for accurate results, one can choose AND based PFD but it consumes more power. The NOR based PFD shows improved performance in terms of power dissipation and RMS noise. Even though the NOR PFD requires 22 transistors, it gives better in RMS noise suppression and reduction in power dissipation. The NOR based PFD also eliminates the missing edge and the phase ambiguity problems. The simulation results and the parameters are calculated using the Mentor Graphics tool at 90nm CMOS Technology. The NOR PFD offers less power dissipation of around 6% to that of AND PFD and 3% to that of NAND PFD. The RMS Noise was also reduced by 30% and 45% to that of AND PFD and NAND PFD respectively for VUP and 42% and 49% to that of AND PFD and NAND PFD respectively for VDN. If the accuracy and area occupied can be slightly ambiguous, then NOR PFD proves to be a best choice. The NAND PFD based PLL has optimum delay and less power dissipation i.e., 50.2% less than that of NOR PFD based PLL which is 25.3% less than that of AND PFD based PLL Hence for low power PLL designs, we choose the design of Type-II PLL

References

  1. Lakshmi Narayana, K.Neelima, “CMOS Dual Loop PLL with Improved Noise Performance and Reduced Power Dissipation”, i-Manager’s Journal on Electronics Engineering, Vol. 6, No. 3, pp. 28 – 35, March-May, 2016.
  2. Lakshmi Narayana, K.Neelima, “Low noise CMOS Dual Loop PLL with Reduced Power dissipation”,National Conference on Current Trends in Science and Technology NCCTST-2016, SS Publications, 8 th May 2016, pp. 116-119, ISSN: 2395-7964.
  3. Rajesh, K.Neelima, “Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18μm CMOS Technology”, i-Manager’s Journal on Circuits and Systems, Vol. 4, No. 1, pp. 12 – 15, December 2015 – January 2016.
  4. Rajesh, K.Neelima, “Design of Wideband Sub-Harmonic Receiver Front-End Using 0.18μm Bipolar Technology”,National Conference on Current Trends in Science and Technology NCCTST-2016, SS Publications, 8 th May 2016, pp. 95-100, ISSN: 2395-7964.
  5. Neelima Koppala, G.Madhavilatha, N. Suguna, “Design and Assessment of CMOS PFDs for Implementation in PLL“, International Conference on Advanced Communication Systems, ICACS2K17, SV Engineering College for Women, Karakambadi road, Tirupati, 20-22 October 2017.
  6. Raj Nandini, Himadri Singh Raghav, B.P.Singh, “Comparison of Phase Frequency Detectors by Different Logic Gates,”International Journal of Innovative Technology and Exploring Engineering (IJITEE), Volume-2, Issue-5, April 2013, ISSN: 2278-3075, pp 150-153.
  7. Rajesh A. Dabhi, Bharat H. Nagpara, “Design and implementation of Phase Frequency Detector Using Different Logic Gates in 45nm CMOS Process Technology,” KIET International Journal of Communications & Electronics (KIET IJCE), Volume. No. 2, Issue No. 1, Jan –April 2014, ISSN: 2320 – 8996, pp 14-17.
  8. Ching-Che Chung and Chen-Yi Lee, “A New DLL-Based Approach for All-Digital Multiphase Clock Generation,” IEEE Journal of Solid -State Circuits, vol. 39, no 3, March 2004, pp469-475.
  9. B. Rashmi and Siva S. Yellampalli, “Design of Phase Frequency Detector and Charge Pump for High Frequency PLL,” International Journal of Soft Computing and Engineering, vol.2, Issue-2, May 2012, pp 88-92.
  10. Khare, N.Khare, P. Deshpande and V. Kulhade , “Phase Frequency Detector of Delay Locked Loop at High Frequency,” lCSE Proc.2008, Johor Bahru, Malaysia , pp 113-116.
  11. Lule, M.A.Gaikwad and V.G.Nasre, “Low Power 0.18um CMOS phase frequency detector,” International Journal of Emerging Technology and Advanced Engineering, vol. 2, July 2012, pp 211-214.
  12. Evan Lee Eschenko “A low power prescaler, phase frequency detector and charge pump for a 12 GHz frequency synthesizer,” A Thesis of Master of Science, Office of Graduate Studies of Texas A&M University, Dec 2007.
  13. Lule and V.Nasre, “Area efficient 0.18um CMOS phase frequency detector for high speed PLL”, International Journal of Engineering Scientific and Research Publication, vol.2, Feb.2012, pp 1-3.
  14. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, 2nd ed., Prentice Hall, 2003.
  15. Satyabh Mishra, (Aug 2012), Design of Charge Pump Phase Locked Loop.

974 total views, no views today

Download PDF File

About the author: admin