Novel Method to Compute Cube Confirming Low Device Utilization on FPGA

Author Name(s): Avinash Patil, S C Patil
Author Email: avispatil@yahoo.co.uk

Abstract

The contribution made by authors in a calculation of a cube of a number includes the digital architectures leading to a computation of cube of an 8- bit binary number which produces the result with reduced hardware utilization on FPGA. The cube is a prominent operation required in many mathematical operations, signal and digital image processing applications. The cube also required in many cryptographic applications as well as trigon arithmetic operations such as taylor series and Mclauren series. The conventional method of finding the cube of a number is faster but required dedicated multiplier block on FPGA and or a large amount of digital gate level resource. The architectural novelty is proposed which can be used at gate level as well as algorithmic level. The cube proposed by authors include features of Vedic mathematics Anurupya sutra, Vertical and crosswise sutra also used, leading to a new better architecture. The cube operation is carried out in VHDL and is compared over conventional as well as Vertical and crosswise based multiplier architectures and provide out better in terms of area and speed optimization. The targeted device used is Spartan XC3S400PQ208 on Xilinx platform.It is observed that the area optimization is achieved with proposed architecture at 2131 gate count compared over 2250 with Vertical and crosswise based cube operation and 8000 gate count with conventional cube calculation method whereas speed enhancement registered over Vertical and crosswise method as proposed method reports 38.348 ns and second one report 43.309 ns.

Introduction

The cube of a number is mathematically its third power, means if b is a number then its cube is the number b multiplier by itself three times. And the result is represented as given in equation 1. b3 = b × b × b. (1) And the same is calculated as a square of a number multiplied by b directly as given in equation 2. b3 = b × b2. (2) The same equations is also a formula for calculating the volume of a cuboid shape with having length, breadth, and height as b. Cube is an odd function as its output is as given in equation 3. (−b)3 = −(b3). (3) As the cube is an odd function it gives the graph which is a parabola in nature and is plotted against b verses b3 as shown in Fig 1. The graph shows that the curve has no axis of symmetry.

Conclusion

The cube operation implemented on Xilinx platform for a targeted device Spartan3 XC3S400PQ208. And the results were generated for conventional method, cube calculation with VC based multiplier and cube calculation by Anurupya sutra with VC based multiplier. The results obtained are compared and it is reported as the proposed method is proved better compared with rest two methods when it comes to device utilization and for speed provides marginal benefits. The area optimization is achieved with proposed architecture at 2131 gate count compared over 2250 with Vertical and crosswise based cube operation and 8000 gate count with conventional cube calculation method whereas speed enhancement registered over Vertical and crosswise method as proposed method reports 38.348 ns and second one report 43.309 ns

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