A Fast and Optimized Architecture to Perform Multi-Bit Permutation Operation

Author Name(s): Sushma Wadar, D S Bormane
Author Email: sushma97in@yahoo.co.in

Abstract

The advanced bit processing operations implemented in the microprocessors and microcontrollers very inefficient. Normally programming techniques are used to emulate the complex bit-related operations. The bit manipulation functions are every now and then required in the areas that are eventually becoming very important. This paper is proposing a techniques which can directly support these bit operations in the form of multimedia shifter unit that can implement standard shifter operations in microprocessors and controllers. The design of the proposed shifter unit is based on the butterfly and inverse butterfly circuits. We show how the proposed design for new shiftes can implement the standard multi-bit scatter and deposit functions found in some processors. The technique proposed in this paper for performing the two operations is based on only Mux. The design of Shifter-Permute functional unit is very challenging work towards its power consumption, speed and area. We have implemented 8-bit Shift-Permute functional unit for bit manipulation and have analyzed the proposed design with the existing design in terms of power consumption, speed and area. Here the circuits are implemented and analyzed by using VHDL and is synthesized by using Xilinx ISE and the targeted device used is Vertex 4 FPGA xc4vlx15-12-sf363 and the same is reflected in the mathematical model purposed for each circuit.

Introduction

Todays general purpose processors are designed with special instructions for multimedia applications [1]. They are provided with larger sets of multimedia instructions as compared to the earlier generation processors. Consequently, providing efficient multimedia hardware has become an important design task.[12] The multi-bit scatter and gather operations for microprocessors and microcontrollers have not been considered and implemented thoroughly as integer and floating-point arithmetic and data transfer operations. The design of the microprocessors is basically around the processing of words. This is the main reason that bit-level operations are typically not as well supported by current word-oriented microprocessors and microcontrollers.[11] AND, OR, XOR and NOT are the basic bit-oriented logical operations implemented by the Arithmetic Logic Unit (ALU), which is a very important functional unit of a controller or a processor. The very regular operations like shift and rotate where all bits in an operand change their place by the same value, are typically supported by a separate shifter functional unit.[3] [4] [9] The emerging applications, like biometrics, imaging and cryptography need advanced multi-bit manipulation operations. These bit-manipulation operations can be implemented in a single circuit using only multiplexers or demultiplexers or circuit including both.

Conclusion

It is expected to mention here, that we have referred the implementation methodology from reference number[11] and implemented it in the same technological environments, Vivado 2015.4 and the performance parameters such as area in terms of LUTs, delay in nanoseconds and area delay product are compared. The extract and deposit functions can be implemented using single circuit design only. The results indicate that  proposed circuit uses less LUTs for both the operations as compared to the separate circuits for each operation. The delay is slightly increased by 0.75ns, due to data reversal circuit which is added in the circuit which is negligible. This new circuit designed and implemented using dual data path proves out to be efficient functional unit.

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